You can use read_verilog or the modern analyze and elaborate flow. The latter is preferred as it allows for better error checking and parameter passing.
# Read all Verilog files read_verilog rv32i_core.v alu.v regfile.v controller.v -work WORK synopsys design compiler tutorial 2021
Before starting, ensure you have the RTL code, standard cell libraries, and a Synopsys Design Constraints (SDC) file. You can use read_verilog or the modern analyze
You can read Verilog or VHDL.
write_sdc $db_dir/$DESIGN_NAME.sdc
Be careful using set_dont_touch on modules, as it prevents DC from optimizing across boundaries. ensure you have the RTL code